TSMC has announced to the public that its N2P and N2X process technologies have been fully updated to match popular EDA tools and selected 3rd-party IPs. In short, they are ready to bring 2nm chips into physical existence.
Revealed at the European Open Innovation Platform (OIP) forum last week, the N2-series brings brand new enhancements to the table including nanosheet gate-all-around (GAA) transistors and super-high-performance metal-insulator-metal (SHPMIM) capacitors to create even more flexibility in terms of performance and power efficiency through channel width adjustments for the former, while the latter is in charge of delivering stable power supply with on-chip decoupling support, with more than 2x the capacity density of previous generations and reduces sheet resistance and via resistance by 50%.
Although these advancements in fabrication technology benefit the whole N2-series nodes, TSMC listed N2P to have a higher degree of merit such as up to 10% lower power consumption assuming fixed transistor count and frequency or up to 10% higher performance gain at the same power level. Compatibility is also a key factor here as N2P and N2x can be shifted seamlessly between themselves, allowing more wriggle room in client talks.
For EDA tools, the Taiwanese giant expressed certifications towards Cadence, Synopsys, Siemens EDA, and Ansys inclusive of simulation and electromigration programs has been completed as well and 3rd-party IPs are now available in pre-silicon design kit form from vendors including TSMC, Alphawave, ABI, Cadence, Synopsys, M31, and Silicon Creations. The release of these pre-silicon design kits in Q4 2024 aligns well with development timelines.
At the current phase, they are still prioritizing the safer bet as in yield rates by refining the entire process economically and technically before entering mass production.
